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- /* NCR53C825.h */
- /*
- * NCR53C825.h
- * Copyright © 1994 Apple Computer Inc. All rights reserved.
- */
- /* .___________________________________________________________________________________.
- | This is a private interface file for the sample driver. It contains configuration |
- | parameters, driver-specific global definitions, and function prototypes. |
- | This interface file contains all hardware-specific data and won't make much sense |
- | without the NCR documemtation. |
- .___________________________________________________________________________________.
- */
-
- #ifndef __NCR53C825__
- #define __NCR53C825__
- /*
- * TEST_DRIVER is set TRUE by the test function. When non-zero it blocks definition
- * of the driver's chip-access functions.
- */
- #ifndef TEST_DRIVER
- #define TEST_DRIVER 0
- #endif
-
- /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
- * The PerRequestRecord is used for each NCR Script operation. If we ever support
- * multiple independent transactions -- to support disconnect/reselect for example,
- * this structure must be replicated on a per-transaction basis. Currently, it
- * has two components: the table used by the NCR Script processor and the mapping
- * vector that the Macintosh operating system uses to map memory between logical
- * and physical addresses. In order to simplify the sample driver, we do not
- * support scatter-gather I/O - this is primarily a function of not wanting to
- * write an elaborate script. Thus, our use of a MappingTable is mostly overkill.
- */
-
- /*
- * The Table is used for NCR "table-indirect" operations. Note: the table must
- * be allocated on a 32-bit address boundary. Note that the address is a
- * longword-swapped PhysicalAddress as the NCR chip wants it in little-endian format.
- */
- struct Table {
- ByteCount byteCount; /* Data transfer count */
- UInt32 address; /* Data transfer address */
- };
- typedef struct Table Table, *TablePtr;
-
- /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
- * Define phase bits - DATO..MSGI are normal SCSI phases. The additional values are
- * aretificial. The script writes the current phase (real or artificial) into the
- * SCRATCHA register, where it can be retrieved by the interrupt handler. This is
- * used to recover from variable-length reads where the user buffer length is greater
- * than the target intents to transmit.
- */
- enum {
- DATO = 0, /* Data output (host -> device) */
- DATI = 1, /* Data input (device -> host) */
- CMD = 2, /* Command */
- STS = 3, /* Status */
- RESO = 4, /* Reserved out -- not used */
- RESI = 5, /* Reserved in -- not used */
- MSGO = 6, /* Message output */
- MSGI = 7, /* Message input */
- ARB_SEL = 8 /* Arbitration "phase" */
- };
- #define kScsiMsgAbort 0x06 /* Message byte to abort (possibly) a target */
-
- /*
- * Offsets into the SCSI Script. These are added to GLOBAL.scriptPhysicalMapping[0]
- * to get the value to store into the NCR Chip's script address. The memory test
- * and interrupt tests use a script that is constructed on-the-fly.
- */
- typedef enum {
- kBusResetScript = 0x08, /* Execute the bus reset script */
- kBusResetScriptRestart = 0x10, /* Restart the bus reset script after delay */
- kSCSICommandScript = 0x18, /* Execute the normal SCSI command script */
- kSCSIRundownScript = 0x20, /* Restart at I/O rundown (failure) script */
- kSCSIRestartScript = 0x28, /* Restart at main phase loop */
- kSCSITestISRScript = 0x01, /* Artificial value to indicate ISR test */
- kSCSITestMemoryScript = 0x02 /* Artificial value to indicate memory test */
- } ScriptSelector;
-
- /*
- * Values for the NCR INT operation. Before jumping to the failure sequence, the
- * script interrupts to log the failure for debugging.
- */
- enum {
- kIntNeedAnotherPreparation = 10000, /* Expected: need to PrepareMemoryForIO */
- kIntFailStrangePhase, /* 10001 Bug: unknown phase at phase loop */
- kIntDataPhaseExpected, /* 10002 At 'Data', but not in data phase */
- kIntPreparationFailed, /* 10003 CTEST == 0 after prep restart */
- kIntDataOutNoData, /* 10004 CTEST not == 2 at DATO phase */
- kIntDataInNoData, /* 10005 CTEST not == 1 at DATI phase */
- kIntNotMsgInAfterStatus, /* 10006 STS phase must be followed by MSGI */
- kIntLastStatusWithoutComma
- };
-
- /*
- * This is the data that the Script processor accesses (by DMA initiated from the
- * PCI bus). The arrows indicate the direction of data flow vis-a-vis the script.
- * Note: the deviceID and dataTables must be on longword boundaries.
- */
- struct ScriptData {
- /*
- * deviceIDTable must be the first location in the script data area.
- */
- Table deviceIDTable; /* -> Target id (longword aligned) */
- Table idMsgTable; /* -> ARB/ATN Msg Out byte */
- Table commandTable; /* -> SCSI command and length */
- Table dataTable; /* -> User data */
- Table statusTable; /* -> Status byte */
- Table completeTable; /* -> Command Complete Msg In byte */
- Table bitBucketInTable; /* -> Bit bucket for input phases */
- Table bitBucketOutTable; /* -> Bit bucket for output phases */
- Table ignoredMsgTable; /* -> To read uninteresting msg's */
- unsigned char scsiCommand[12]; /* -> SCSI Command copied here */
- unsigned char idMsgByte; /* -> Initialization message byte */
- unsigned char statusByte; /* <- Status phase result */
- unsigned char commandCompleteByte; /* <- Command complete result */
- unsigned char bitBucketInByte; /* <- DATI bit-bucket */
- unsigned char bitBucketOutByte; /* -> DATO bit-bucket */
- unsigned char ignoredMsgInByte; /* <- MSGI bit-bucket (ignored msg) */
- OSErr ncrStatus; /* Non-zero on failure */
- };
- typedef struct ScriptData ScriptData, *ScriptDataPtr;
-
- /*
- * When the NCR chip interrupts, the interrupt service routine retrieves volatile
- * information from the NCR chip and stores it in the request block. In a real
- * driver, these might be local variables in the interrupt service routine. They
- * are here so they can be dumped for post-mortem debugging. The hex values are
- * the register addresses in the NCR chip.
- */
- struct NCRRegisterShadow {
- unsigned long residualTransferCount; /* Bytes remainomg at phase error */
- unsigned long dbc; /* 0x24 data byte count value */
- unsigned long dsp; /* 0x2C Script data pointer */
- unsigned long dsps; /* 0x30 SCSI interrupt condition */
- unsigned char scntl1; /* 0x01 SCSI Control One */
- unsigned char istat; /* 0x14 Interrupt status */
- unsigned char dstat; /* 0x0C DMA interrupt status */
- unsigned char sist0; /* 0x42 SCSI interrupt status zero */
- unsigned char sist1; /* 0x43 SCSI interrupt status one */
- unsigned char socl; /* 0x09 SCSI output control lines */
- unsigned char sbcl; /* 0x0B SCSI bus control lines */
- unsigned char sstat0; /* 0x0D SCSI status zero */
- unsigned char sstat1; /* 0x0E SCSI status one */
- unsigned char sstat2; /* 0x0F SCSI status two */
- unsigned char dfifo; /* 0x20 dma fifo byte counter */
- /*
- * ctest3 and stest3 are only read to clear a dma fifo non-empty error condition.
- */
- unsigned char ctest3; /* 0x1B Chip Test three */
- unsigned char stest3; /* 0x4F SCSI Test three */
- short scriptPCOffset; /* dsp - gNCRScript */
- };
- typedef struct NCRRegisterShadow NCRRegisterShadow;
-
- /*
- * This defines the data that is retained for individual transactions. A pointer to
- * this structure is passed to the interrupt service routine.
- *
- * Note: PerRequestData must be allocated on a 32-bit address boundary - the NCR chip
- * requires table indirect records to be longword aligned. PerRequestData is defined
- * in the NCR53C850.h header file. If we extend the driver to permit multiple
- * simultaneous transfers, we'll need a PerRequestData structure for each simultaneous
- * execution thread. As these must be allocated from "task" context, we may allocate
- * a "pool" of PerRequestData records when the driver is opened. For now, we allocate a
- * single PerRequestData record.
- */
- #if STRUCTALIGNMENTSUPPORTED
- #pragma options align=power
- #endif
- struct PerRequestData {
- ScriptData scriptData; /* Data shared with the NCR chip */
- NCRRegisterShadow shadow; /* The NCR registers at interrupt */
- /*
- * This data is changed with each PBRead/PBWrite/PBControl I/O request.
- */
- TimerID timerID; /* Interrupt Timer ID */
- AddressSpaceID addressSpaceID; /* From the DoDriverIO call */
- IOCommandID ioCommandID; /* From the DoDriverIO call */
- ParmBlkPtr pb; /* From the DoDriverIO call */
- ScriptSelector scriptSelector; /* SCSI or Bus Reset script */
- Duration watchdogTimeout; /* -> Msec timeout, zero = none */
- /*
- * This data is initialized when the PerRequestData record is created.
- * perRequestIOTable Preparation table for the perRequestRecord
- * scsiIOTable Preparation table for the caller's SCSI command.
- * scsiMapSize Number of elements in the scsiPhysicalMapping vector.
- */
- ItemCount scsiMapSize;
- IOPreparationTable perRequestIOTable; /* Preparation for this record */
- /*
- * This augments the perRequestIOTable to support partial preparation.
- */
- IOPreparationTable scsiIOTable; /* PrepareMemoryForIO information */
- SoftwareInterruptID nextDMAInterruptID; /* Used for subsequent preparations */
- LogicalAddress userBufferStart; /* User area yet to prepare */
- LogicalAddress userBufferEnd; /* Used to check I/O overrun */
- ByteCount amountToTransfer; /* Amount remaining to prepare */
- ByteCount dmaFirstPrepared; /* This partial I/O start offset */
- ByteCount dmaLengthPrepared; /* This partial I/O transfer count */
- ItemCount physicalMapIndex; /* -> physicalMapping[] for DMA */
- /*
- * Script physical addresses (from their respective IOPreparation tables).
- */
- UInt32 scriptBaseAddress; /* Script start address */
- UInt32 scriptPtr; /* PhysicalAddress of the script */
- UInt32 scriptDataPtr; /* PhysicalAddress of script data */
- /*
- * physicalMapTables holds the physical mapping tables for the user I/O requests
- * and for the PerRequestData record itself.
- */
- ItemCount scsiMapEntries; /* Elements for user SCSI requests */
- PhysicalMappingTablePtr physicalMapTables; /* PhysicalMapping for this request */
- /*
- * This area is used to create a dynamic script for memory and interrupt scripts.
- * The stateTag is copied from the NCRCSCIParam block in the IOParam block.
- */
- UInt32 memoryMoveScript[5];
- };
- #if STRUCTALIGNMENTSUPPORTED
- #pragma options align=reset
- #endif
- typedef struct PerRequestData PerRequestData, *PerRequestDataPtr;
-
- /*
- * PCI configuration definitions - I got these by installing the board and dumping
- * the property list. They differ slightly from the printed documentation. Only the
- * device name and kPCIRevisionID are used.
- */
- #define kPCIVendorID 0x1000 /* 00 15- 0 Registered vendor ID */
- #define kPCIClassCode 0x00010000 /* 08 31- 8 Registered class code */
- #define kPCIRevisionID 0x02 /* 08 7- 0 Registered revision ID */
- #define kPCIRegisterSize 0x100 /* Size of the I/O and/or Mem area */
- /*
- * These are offsets within the Configuration Register area that Open Firmware uses
- * to determine the register mapping. The driver can use the I/O and/or memory base
- * registers. Expansion rom is not used, but could be used by a utility that stores
- * a driver into the NCR flash rom.
- */
- #define kPCIIOBaseRegister 0x10 /* I/O base address in Config Reg's */
- #define kPCIMemoryBaseRegister 0x14 /* Memory base address in Config Reg's */
- #define kPCIExpansionROMRegister 0x30 /* Expansion rom base in Config Reg's */
- /*
- * These definitions specify the hardware we support. kPCIDeviceID is in the
- * configuration register. kPCIChipRevision is read from an on-chip register.
- * The only difference between the two versions is the device name string, device
- * id, and the chip revision. To do: build the driver core as a shared library,
- * build two stub drivers with independent DriverDescription structures, and
- * update the chip revision test.
- */
- #if 0 /* NCR 53C825 */
- #define kPCIDeviceNamePString "\ppci1000,3" /* Name string - StringPtr */
- #define kPCIDeviceNameCString "pci1000,3" /* Name string - C string */
- #define kPCIDeviceID 0x0003 /* 00 31-16 Registered device ID */
- #define kPCIChipRevision (bit5) /* CTEST3 value */
- #elif 1 /* NCR 53C815 */
- #define kPCIDeviceNamePString "\ppci1000,4" /* Name string - StringPtr */
- #define kPCIDeviceNameCString "pci1000,4" /* Name string - C string */
- #define kPCIDeviceID 0x0004 /* 00 31-16 Registered device ID */
- #define kPCIChipRevision (bit5 | bit4) /* CTEST3 value */
- #elif 0 /* NCR 53C825 with AAPL name */
- #define kPCIDeviceNamePString "\pAAPL,NCR8250S" /* Name string - StringPtr */
- #define kPCIDeviceNameCString "AAPL,NCR8250S" /* Name string - C string */
- #define kPCIDeviceID 0x0003 /* 00 31-16 Registered device ID */
- #define kPCIChipRevision (bit5) /* CTEST3 value */
- #else
- /* Unknown */
- #endif
- #if 0
- /*
- * As part of our "manufacturing process" we have changed the name by updating
- * the on-board firmware.
- */
- #undef kPCIDeviceNamePString
- #undef kPCIDeviceNameCString
- #define kPCIDeviceNamePString "\pAAPL,NCR8250S" /* Name string - StringPtr */
- #define kPCIDeviceNameCString "AAPL,NCR8250S" /* Name string - C string */
- #endif
-
- #define kBusResetDuration (50) /* Bus Reset lasts 50 microseconds */
- #define kMaxSCSIInitiatorID 7 /* Change this for wide support */
- #define kSCSIInitiatorID 7 /* Our default SCSI bus ID */
-
- /*
- * The first time that a script is executed, labels will be resolved to their
- * pc-relative values. To make this work, the first and last instructions of each
- * each script must be marked with Label instructions. The script-runner uses
- * kScriptStartLabel to identify un-resolved scripts.
- */
- #define kScriptStartLabel '++++'
- /*
- * This is a little-endian "INT" instruction for the memory and interrupt tests.
- */
- #define kIntOpcode 0x00000898
-
- #ifndef REZ
-
- #define bit0 0x00000001
- #define bit1 0x00000002
- #define bit2 0x00000004
- #define bit3 0x00000008
- #define bit4 0x00000010
- #define bit5 0x00000020
- #define bit6 0x00000040
- #define bit7 0x00000080
- #define bit8 0x00000100
- #define bit9 0x00000200
- #define bit10 0x00000400
- #define bit11 0x00000800
- #define bit12 0x00001000
- #define bit13 0x00002000
- #define bit14 0x00004000
- #define bit15 0x00008000
- #define bit16 0x00010000
- #define bit17 0x00020000
- #define bit18 0x00040000
- #define bit19 0x00080000
- #define bit20 0x00100000
- #define bit21 0x00200000
- #define bit22 0x00400000
- #define bit23 0x00800000
- #define bit24 0x01000000
- #define bit25 0x02000000
- #define bit26 0x04000000
- #define bit27 0x08000000
- #define bit28 0x10000000
- #define bit29 0x20000000
- #define bit30 0x40000000
- #define bit31 0x80000000
-
-
- /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
- * Configuration Registers
- *
- * This table gives offsets to registers in the NCR53C825 chip. The configuration
- * registers (0..128) are only available during configuration cycles. All values
- * are hex byte offsets. Note:
- * cl Configuration Longword
- * cw Configuration Short (16-bit) word
- * cb ConfigurationByte
- */
- enum {
- kConfigStart = 0x00,
- cwVendorID = 0x00, /* 0x1000 */
- cwDeviceID = 0x02, /* 0x0003 */
- cwCommand = 0x04,
- cwStatus = 0x06,
- clClassCodeAndRevID = 0x08,
- clHeaderAndLatency = 0x0C,
- clBaseAddressZero = 0x10, /* I/O Base address */
- clBaseAddressOne = 0x14, /* Memory Base address */
- clExpansionRomAddr = 0x30,
- clLatGntIntPinLine = 0x3C, /* Max_Lat, Max_Gnt, Int. Pin, Int. Line */
- kConfigEnd = 0x40
- };
-
- /*
- * 0x04 cwCommand Command Register (read/write)
- */
- enum {
- cwCommandSERREnable = bit8,
- cwCommandEnableParityError = bit6,
- cwCommandEnableBusMaster = bit2, /* Set this on initialization */
- cwCommandEnableMemorySpace = bit1, /* Respond at Base Address One if set */
- cwCommandEnableIOSpace = bit0 /* Respond at Base Address Zero if set */
- };
- /*
- * 0x06 cwStatus Status Register (read/write)
- */
- enum {
- cwStatusDetectedParityError = bit15, /* Detected from slave */
- cwStatusSignaledSystemError = bit14, /* Device asserts SERR/ signal */
- cwStatusMasterAbort = bit13, /* Master sets when transaction aborts */
- cwStatusReceivedTargetAbort = bit12, /* Master sets when target-abort */
- cwStatusDEVSELTimingMask = (bit10 | bit9), /* DEVSEL timing encoding R/O */
- cwStatusDEVSELFastTiming = 0,
- cwStatusDEVSELMediumTiming = bit9,
- cwStatusDEVSELSlowTiming = bit10,
- cwStatusDataParityReported = bit8
- };
-
-
- /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
- * Operating Registers
- *
- * These registers control the 53C825 operation. All values are hex byte offsets.
- * You'll need to consult the NCR documentation for register sizes and uses.
- */
- enum {
- kRegisterBase = 0x80, /* Offset from config memory base */
- SCNTL0 = kRegisterBase + 0x00, /* b RW SCSI Control 0 */
- SCNTL1 = kRegisterBase + 0x01, /* b RW SCSI Control 1 */
- SCNTL2 = kRegisterBase + 0x02, /* b RW SCSI Control 2 */
- SCNTL3 = kRegisterBase + 0x03, /* b RW SCSI Control 3 */
- SCID = kRegisterBase + 0x04, /* b RW SCSI Chip ID */
- SCXFER = kRegisterBase + 0x05, /* b RW SCSI Transfer */
- SDID = kRegisterBase + 0x06, /* b RW SCSI Destination ID */
- GPREG = kRegisterBase + 0x07, /* b RW General Purpose Bits */
- SFBR = kRegisterBase + 0x08, /* b RW SCSI First Byte Received */
- SOCL = kRegisterBase + 0x09, /* b RW SCSI Output Control Latch */
- SSID = kRegisterBase + 0x0A, /* b RO SCSI Selector ID */
- SBCL = kRegisterBase + 0x0B, /* b RW SCSI Bus Control Lines */
- DSTAT = kRegisterBase + 0x0C, /* b RO DMA Status */
- SSTAT0 = kRegisterBase + 0x0D, /* b RO SCSI Status 0 */
- SSTAT1 = kRegisterBase + 0x0E, /* b RO SCSI Status 1 */
- SSTAT2 = kRegisterBase + 0x0F, /* b RO SCSI Status 2 */
- DSA = kRegisterBase + 0x10, /* l RW Data Structure Address */
- ISTAT = kRegisterBase + 0x14, /* b RW Interrupt Status */
- CTEST0 = kRegisterBase + 0x18, /* b RW Chip Test 0 */
- CTEST1 = kRegisterBase + 0x19, /* b RW Chip Test 1 */
- CTEST2 = kRegisterBase + 0x1A, /* b RO Chip Test 2 */
- CTEST3 = kRegisterBase + 0x1B, /* b RO Chip Test 3 */
- TEMP = kRegisterBase + 0x1C, /* l RW Temporary Stack (Return Stack) */
- DFIFO = kRegisterBase + 0x20, /* b RW DMA Fifo */
- CTEST4 = kRegisterBase + 0x21, /* b RW Chip Test 4 */
- CTEST5 = kRegisterBase + 0x22, /* b RW Chip Test 5 */
- CTEST6 = kRegisterBase + 0x23, /* b RW Chip Test 6 */
- DBC = kRegisterBase + 0x24, /* l RW DMA Byte Counter (bits 23-0) */
- DCMD = kRegisterBase + 0x27, /* b RW DMA Command */
- DNAD = kRegisterBase + 0x28, /* l RW DMA Next address for data */
- DSP = kRegisterBase + 0x2C, /* l RW DMA Scripts pointer (Script PC) */
- DSPS = kRegisterBase + 0x30, /* l RW DMA Scripts Pointer Save */
- SCRATCHA = kRegisterBase + 0x34, /* l RW General purpose scratch A */
- DMODE = kRegisterBase + 0x38, /* b RW DMA Mode */
- DIEN = kRegisterBase + 0x39, /* b RW DMA Interrupt Enable */
- DWT = kRegisterBase + 0x3A, /* b RW DMA Watchdog Timer */
- DCNTL = kRegisterBase + 0x3B, /* b RW DMA Control */
- ADDER = kRegisterBase + 0x3C, /* l RO Sum output of internal adder */
- SIEN0 = kRegisterBase + 0x40, /* b RW SCSI Interrupt Enable 0 */
- SIEN1 = kRegisterBase + 0x41, /* b RW SCSI Interrupt Enable 1 */
- SIST0 = kRegisterBase + 0x42, /* b RO SCSI Interrupt Status 0 */
- SIST1 = kRegisterBase + 0x43, /* b RO SCSI Interrupt Status 1 */
- SLPAR = kRegisterBase + 0x44, /* b RW SCSI Longitudinal Parity */
- SWIDE = kRegisterBase + 0x45, /* b RO SCSI Wide Residual Data */
- MACNTL = kRegisterBase + 0x46, /* b RW Memory Access Control */
- GPCNTL = kRegisterBase + 0x47, /* b RW General Purpose Control */
- STIME0 = kRegisterBase + 0x48, /* b RW SCSI Timer 0 */
- STIME1 = kRegisterBase + 0x49, /* b RW SCSI Timer 1 */
- RESPID0 = kRegisterBase + 0x4A, /* b RW Response ID 0 */
- RESPID1 = kRegisterBase + 0x4B, /* b RW Response ID 1 */
- STEST0 = kRegisterBase + 0x4C, /* b RO SCSI Test 0 */
- STEST1 = kRegisterBase + 0x4D, /* b RO SCSI Test 1 */
- STEST2 = kRegisterBase + 0x4E, /* b RW SCSI Test 2 */
- STEST3 = kRegisterBase + 0x4F, /* b RW SCSI Test 3 */
- SIDL = kRegisterBase + 0x50, /* w RO SCSI Input Data Latch */
- Reserved0 = kRegisterBase + 0x52, /* w Reserved */
- SODL = kRegisterBase + 0x54, /* w RW SCSI Output Data Latch */
- Reserved1 = kRegisterBase + 0x56, /* w Reserved */
- SBDL = kRegisterBase + 0x58, /* w RO SCSI Bus Data Lines */
- Reserved2 = kRegisterBase + 0x5A, /* w Reserved */
- SCRATCHB = kRegisterBase + 0x5C, /* l RW General Purpose Scratch B */
- kIORegisterMax = kRegisterBase + 0x60 /* Off the end of the registers */
- };
-
- /*
- * NCR chip access functions
- */
- typedef enum {
- kNCRResetChipInitialize = 0, /* Called on driver initialize */
- kNCRResetChipTerminate, /* Called on driver termination */
- kNCRResetChipPowerDown, /* Handle PBControl driverPowerLow */
- kNCRResetChipPowerUp, /* Handle PBControl driverPowerHigh */
- kNCRStopCurrentScript, /* Handle KillIO request */
- kNCRLastCommandID /* Enum trailing comma blocker */
- } NCRChipResetCommand;
-
-
- #endif /* If not REZ */
- #endif /* __NCR53C825__ */